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sbl_uni: prog 200K samples, DDRHI-ext2/3 creep runway

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SashegDev
2026-09-15 02:33:24 +00:00
parent 36c502dc39
commit 9f19c926cb
1 changed files with 3 additions and 1 deletions
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tools/sbl_uni.py
+3 -1
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@@ -32,6 +32,8 @@ RAMS = [
(0x08600000, 0x00010000), # IMEM (0x08600000, 0x00010000), # IMEM
(0x08610000, 0x00FF0000), # DDRHI (QEMU parity; IMEM-stack spillover) (0x08610000, 0x00FF0000), # DDRHI (QEMU parity; IMEM-stack spillover)
(0x09600000, 0x01000000), # DDRHI-ext (tier spillover; zeros) (0x09600000, 0x01000000), # DDRHI-ext (tier spillover; zeros)
(0x0A600000, 0x01000000), # DDRHI-ext2 (creep runway; zeros)
(0x0B600000, 0x01000000), # DDRHI-ext3 (creep runway; zeros)
(0x80000000, 0x07C00000), # DDRHIGH_A (0x80000000, 0x07C00000), # DDRHIGH_A
(0x87C00000, 0x00800000), # SMEM(+SBL BSS) (0x87C00000, 0x00800000), # SMEM(+SBL BSS)
(0x07800000, 0x000AF000), # leak-sink HI (S12 frame march; (0x07800000, 0x000AF000), # leak-sink HI (S12 frame march;
@@ -149,7 +151,7 @@ def main():
def hook_code(mu, addr, size, data): def hook_code(mu, addr, size, data):
count[0] += 1 count[0] += 1
last[0] = addr last[0] = addr
if count[0] % 2000000 == 0: if count[0] % 200000 == 0:
from unicorn.arm_const import UC_ARM_REG_SP as _SX from unicorn.arm_const import UC_ARM_REG_SP as _SX
print('prog:', count[0], hex(addr), hex(mu.reg_read(_SX)), flush=True) print('prog:', count[0], hex(addr), hex(mu.reg_read(_SX)), flush=True)
_pp = _prev[0] _pp = _prev[0]